1. Field of the Invention
The present invention generally relates to semiconductor apparatus, and more particularly, to semiconductor apparatus which have multichip module configurations.
2. Description of the Prior Art
Recently, an operating frequency used in electronic devices has been increasing to higher than 100 MHz. Accordingly, it is required that semiconductor devices assembled in the electronic devices can operate at such a higher operating frequency.
To meet this requirement, semiconductor devices having multichip-module configurations, in which bare LSI chips are mounted on thin-film multilayer substrates, are widely used.
FIG. 1 shows a cross-sectional view of a conventional semiconductor device 10 having the multichip-module configuration.
The semiconductor device 10 comprises a ceramic base 11, a thin-film multilayer substrate 12, a bare chip 13, a lead 14, and a wire 15, etc. A plurality of bare chips 13 are mounted on the thin-film multilayer substrate 12 by a flip-chip method. The thin-film multilayer substrate 12 comprises a Si substrate 20 and a thin-film multilayer interconnection layer 21 thereof.
The thin-film multilayer interconnection layer 21 has a decoupling capacitance 22 in a bottom side, a plurality of insulating layers 23 and Cu-interconnection patterns 24 which are alternately formed on the decoupling capacitance 22, and a via 25.
The decoupling capacitance 22 suppresses switching noise generated with an operation of the bare chip 13 to stabilize a voltage Vcc. The decoupling capacitance 22 comprises Cu films 30, 31 as a pair of electrodes, and a dielectric layer 32 between the Cu films 30, 31, and has almost the same size as that of the substrate 20.
The insulating layer 23 is made of a mixed polyimide resin which is mixed with photosensitive material. By mixing with the photosensitive material, a complex synthesis reaction between a photosensitive group and a polyimide is not required. Thus, a less-expensive insulating material is produced, making it possible to reduce a cost of the whole device.
The via 25 has a configuration in which three via parts 35, 36, 37 are overlapped at the same position.
The conventional semiconductor device 10 has problems in the thin-film multilayer interconnection layer 21, namely in the decoupling capacitance 22, the Cu-interconnection layer 24, and the via 25.
i) The problem in the decoupling capacitance 22:
The decoupling capacitance needs to be as large as possible to stabilize the voltage. To enlarge the decoupling capacitance, each of the Cu films 30, 31 has a wide area, and the dielectric layer 32 is thinned as much as possible.
Therefore, pinholes easily occur in the dielectric layer 32, and the pinholes cause the Cu films 30, 31 to short. There is thus a problem that a poor decoupling capacitance easily occurs.
ii) The problem in the Cu-interconnection layer 24:
A surface 23a of the insulating layer 23, on which the Cu-interconnection layer 24 is formed, is a coarse face having a 1- to 2-.mu.m-height fine ruggedness, because the photosensitive material is mixed. The Cu-interconnection layer 24 is formed by sputtering Cu, forming a Cu film, and then etching it. In this process, the fine ruggedness affects the sputtering, thus local dispersion of a film thickness occurs in the Cu film. Also in the interconnection pattern 24 formed by the etching, thin parts are locally generated. Therefore, a volume resistivity is enlarged to several times a theoretical value.
As a result of measuring the volume resistivity of the interconnection pattern 24, the ratio was found to be 5.30 .mu..OMEGA.cm. This value is approximately three times the theoretical value of 1.67 .mu..OMEGA.cm. Therefore, when the semiconductor device is operative, a temperature of the interconnection pattern 24 increases abnormally. The increases temperature causes migration to grow, and causes a material of the insulating layer 23 to change in quality, so that insulation of the insulating layer 23 is degraded. This degradation of the insulation of the insulating layer 23 may cause an upper-side interconnection pattern 24 and a lower-side interconnection pattern 24 in the insulating layer 23 to short.
In this case, characteristics of the thin-film multilayer substrate 12 depart from designed values, and as a result, performance of the semiconductor device 10 is degraded.
In a worst case, the interconnection pattern 24 is snapped.
iii) The problem in the via 25:
Because the via parts 35, 36, 37 are formed in the same position, according to the via parts being piled, thin parts occur in the via 25 as indicated by a numeral 38. Those thin parts cause a reliability of the via 25 to be reduced.